Verilog - Gate Level Modelling

Gate Types

We know that a digital logic circuit can be designed by the use of Logic Gates.

Verilog supports all the basic logic gates as predefined primitives. These primitives are instantiated like modules except the fact that they are predefined in verilog (thus they do not need a module definition).

Gate Level Modelling is not the lowest level of abstraction when it comes to modelling hardware, the lowest level is Switch Level Modelling, which we will be discussing later.

There are 14 Logic Gates and 12 Switches predefined in the Verilog HDL to provide the Gate-Level and Switch-Level modeling facility respectively. Modeling with logic gates and switches has the following advantages:

• Gates provide a much closer one-to-one mapping between the actual circuit and the model.
• There is no continuous assignment equivalent to the bidirectional transfer gate.

• N-Input Gates : These are and, nand, or, nor. xor and xnor.
• N-Output Gates : These are not and buf.
• 3 State gates : These are bufif0, bufif1, nitif0 and notif1
• Pull Gates : These are pullup and pulldown

Gate Declaration

A Gate or a Switch instance declaration shall have the following specifications:

• The keyword that names the type of gate or switch primitive
• An Optional Drive Strength
• An Optional Propagation Delay
• An Optional identifier that names each gate or switch instance
• An Optional range for array of instances
• The terminal connection list

Gate Type Specification

A Gate or Switch instance declaration shall begin with the keyword that specifies the gate or switch primitive being used by the instances that follow in the declaration.

Refer below table for the list of Gate and Switch primitives in verilog :

Refer example code below :

Drive Strength Specification

An optional Drive Strength Specification shall specify the strength of the logic values on the output terminals of the gate instance.

The drive strength specification for a gate instance, with the exception of pullup and pulldown, shall have a strehgth1 specification and a strehgth0 specification.

• The strength1 specification shall specify the strength of signals with a logic value 1.
• The strength0 specification shall specify the strength of signals with a logic value 0.

The strength1 specification shall be one of the following keywords : supply1, strong1, pull1, weak1

The strength0 specification shall be one of the following keywords : supply0, strong0, pull0, weak0

Refer example code below :

Delay Specification

An optional delay specification shall specify the propagation delay through the gates and switches in a declaration.

Refer example code below :

Primitive Instance Identifier

An optional name can be given to a gate or switch instance. If multiple instances are declared as an array of instances, an identifier shall be used to name the instances.

Refer example code below :

Range Specification

There are many situations when repetitive instances are required. These instances shall differ from each other only by the index of the vector to which they are connected.

An array of instances shall have a continuous range. One instance identifier shall be associated with only one range to declare an array of instances.

Refer example code below :

Basic Gates

2 or N-Input Gates

The basic logic gates in verilog available as inbuilt primitives for the construction of digital logic are : nand, and, nor, or, xor and xnor.

The symbols for all the above mentioned logic gates are given below :

The Truth Tables of the above 6 logic gates is given below :

Their basic declaration can be seen from code below :

Let us now try making a simple digital logic circuit of the below circuit using Gate Level Modelling :

buf and not gate

buf and not gates have one scalar input and one or more scalar outputs. The last terminal in the port list is connected to the input, other terminals are connected to the outputs.

The inbuilt primitives in verilog for these are buf and not.

The symbols for the buf and not logic gates are given below :

Their Truth Tables is given below :

Their basic declaration can be seen from code below :

bufif1, bufif0, notif1 and notif0 gates

These gates are 3-state logic gates. These four logic gates model three-state drivers. In addition to logic values 1 and 0, these gates can output Z.

These four logic gates shall have one output, one data input, and one control input. The first terminal in the terminal list shall connect to the output, the second terminal shall connect to the data input, and the third terminal shall connect to the control input.

The symbols for the bufifX and notifX logic gates are given below :

Their Truth Tables is given below :

These logic tables for these gates include two symbols representing such unknown results. The symbol L shall represent a result that has a value 0 or Z. The symbol H shall represent a result that has a value 1 or Z. Delays on transitions to H or L shall be treated the same as delays on transitions to X.

Their basic declaration can be seen from code below :

pullup and pulldown sources

Verilog has inbuilt primitives for modelling circuit pullup's and pulldown sources. These primitives are : pullup and pulldown respectively.

A pullup source shall place a logic value 1 on the nets connected in its terminal list. A pulldown source shall place a logic value 0 on the nets connected in its terminal list.

• The signals that these sources place on nets shall have pull strength in the absence of a strength specification.
• If there is a strength1 specification on a pullup source or a strength0 specification on a pulldown source, the signals shall have the strength specified.
• A strength0 specification on a pullup source and a strength1 specification on a pulldown source shall be ignored.

For example refer code example below :