System Tasks for Assertion Control

System Tasks

There are many situations when you want to have a global control over assertions both and module and instance level.

System Verilog provides the following three system tasks to control the evaluation of assertion statements :

• $assertoff : Stops the checking of all specified assertions until a subsequent $asserton. An assertion that is already executing, including execution of the pass or fail statement, is not affected.
• $assertkill : Aborts execution of any currently executing specified assertions and then stop the checking of all specified assertions until a subsequent $asserton.
• $asserton : Re-enables the execution of all specified assertions.

When invoked with no arguments, the system task shall apply to all assertions. When the task is specified with arguments, the first argument indicates levels of the hierarchy. Subsequent arguments specify which scopes of the model to control. These arguments can specify entire modules or individual assertions.

The syntax for these System control tasks is shown below :