SV- Attributes

Attributes

A mechanism is included for specifying properties about objects, statements, and groups of statements in the System Verilog source that can be used by various tools, including simulators, to control the operation or behavior of the tool.

These properties are referred to as attributes.

The syntax for specifying an attribute is shown below :

An attribute_instance can appear in the System Verilog description as a prefix attached to a declaration, a module item, a statement, or a port connection. It can appear as a suffix to an operator or a function name in an expression.

The default type of an attribute with no value is bit, with a value of 1. Otherwise, the attribute takes the type of the expression.

NOTE : If the same attribute name is defined more than once for the same language element, the last attribute value shall be used, and a tool can issue a warning that a duplicate attribute specification has occurred.

example below illustrates how to attach attributes to a case statement:

Refer example below of attaching attribute to a module definition :

Refer example below for attaching attribute to a variable declaration :

Refer example below for attaching attribute to an operator :

Refer example below for attaching attribute to a function call :

Refer example below for attaching attribute to a conditional; operator :