Topics related to Tools and Usages :
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Simulating your SV Design and Testbench and dumping waveforms on all tools (Synopsys VCS / Cadence NCSim / Mentor Questasim)
Generating and Analyzing Code + Functional Coverage for your Design/TB on all tools (Synopsys VCS / Cadence NCSim / Mentor Questasim)
UVM Papers and Implementations :
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Using UVM Virtual Sequencers and Virtual Sequences.
UVM Scoreboards and Architectures.
Collecting UVM Responses (from Monitors) in the TestBench Virtual Sequencer for use in Sequence Checkers.
Design Papers and Implementations :
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FSM Design and Synthesis using System Verilog.
Implementing a Simple APB Slave Block.
Implementing a Simple AHB Slave Block.
Python Script for generating Register RTL Code Block and UVM RAL Register Block (for Verification).
The 4-wire JTAG.
The 2-wire JTAG (cJTAG).